With the ongoing increase in demand for higher System-on-Chip (SoC) I/O speeds, the significance of data rates for chip-to-chip (C2C) and chip-to-module (C2M) communication is becoming more crucial than ever. The adoption of PMA4 has become prevalent in SerDes design, and even the consideration of PAM8 modulation is on the horizon. However, while the relatively simple architecture of NRZ, PAM4, and PAM8 offers advantages, these modulation formats also suffer from suboptimal spectrum efficiency. This challenge is particularly pronounced when limitations in PCB or substrate RF bandwidth act as bottlenecks for achieving desired data throughput performance.

pic1 MIMO-OFDM for IEEE802.3 - 2022 xxxGAUI 100GBd+/LANE Chip-to-Chip connection

Despite leveraging modern digital enhancements like Transmitter Finite Impulse Response (Tx FIR) and Receiver Continuous Time Linear Equalization (CTRL), Feed Forward Equalization (FFE), and Decision Feedback Equalization (DFE), we find ourselves confronted with the limitations of PCB/substrate bandwidth. These limits are evident when Insertion Loss (IL) reaches approximately -50 dB at frequencies around 80 GHz.

Existing solutions have explored doubling the overall data rate by doubling the total number of lanes. However, this approach is constrained by considerations such as silicon size, PCB dimensions, and the total number of I/O ports.

The upcoming era of high-speed I/O is poised to embrace the MIMO-OFDM architecture for SerDes. MIMO-OFDM brings forth a range of three key advantages when compared to NRZ, PAM4, and PAM8 modulation schemes.

1. OFDM employs complex signals that exhibit double the spectrum efficiency when contrasted with real signals of NRZ, PAM4, and PAM8.

2. MIMO demands reduced cross-lane isolation (8x8, 25dB) compared to PAM4’s requirement of >40dB, leading to a more streamlined PCB RF routing design.

3. The utilization of OFDM/QAM1024 results in a throughput that is 3.33 times higher than that achieved by PAM8, with a similar level of bandwidth and SDNR at 32dB.

Existing Highspeed IO/SerDes for C2C, C2M connection

Below picture is the IEEE802.3-2022 attachment unit interface(AUI) to show the PCB insertion loss limitations.

pic2 Attachment Unit Interface(AUI): channel loss challenges

Complex Signal over Real Signal

Below pictures are the illustration of Complex Signal vs. Real Signal. A real signal is a type of signal that only contains real values. In other words, the signal values are real numbers, representing the amplitude or magnitude of the signal at a particular point in time. A complex signal, also known as a complex-valued signal, includes both real and imaginary components. The imaginary component represents a phase shift or angular information that complements the magnitude (real part) of the signal. pic3 The spectrum of a complex signal exhibits an asymmetric between negative and positive components.

pic4 Real signal

Example: Considering the design of Baseband OFDM for bandwidths of 10G/20GHz/40G/80G.

Assume MII datarate=25Gb/s for NRZ and 25GBd/s for PAM4, the AUI one lane RF BW should be greater than 75%*25GHz= 18.75GHz. Let’s pick the 20GHz Baseband BW as the reference point to calculate. 1. I/Q requires 2 lanes if we use the NRZ/PAM4 AUI concept. The Complex signal BW is 40GHz. ADC/DAC clock rate will be 80~100GHz which is doable. 2. We employ 512 subcarriers with an FFT/IFFT size of 512 points. The subcarrier spacing will be 78.125MHz, and the symbol length, excluding the cyclic prefix (CP), will be 12.8ns. 3. Guard Interval (GI) for solving inter-symbol interference (ISI) issue in OFDM system. Three GI strategies we can consider: A. Cyclic prefix (CP) – commonly used in wireless industrial. B. Zero Padding – some coherent system. C. Zero-guard-interval for coherent system. Since GI is the overhead of throughput, smaller GI should be get faster lane speed. Our user case here is the PCB/substrate with length about 1mm~100mm. Even considering if we would use optical fiber CD/PMD model, the GI should be within 0.1ns. 4. Packet length. This could be a complex topic. Let’s assume MAC generate the package and Phy only rapacked it for sending. In this case, package length (how many symbols) will depending on Mac datasize, Phy’s FFT/IFFT engin power, and size of SRAM in SoC to do the calculation.

At end

The MIMO-OFDM SerDes design is poised to be compatible with PAM4 and has the potential to directly facilitate the driving of coherent optical MDI layer for simplifying the module design.

REFERENCES:

[1] IEEE802.3-2022

[2] Considerations on beyond 100G per lane electrical objectives: YuchunLU, Yan ZHUANG

[3] Zero-guard-interval coherent optical OFDM with overlapped frequency-domain CD and PMD equalization: Chen Chen, Qunbi Zhuge, and David V. Plant

[4] The Cyclic Prefix for OFDM

[5] BER PERFORMANCE OF OFDM SYSTEM WITH CYCLIC PREFIX & ZERO PADDING: Prafulla. D. Gawande and Sirddharth. A. Ladhake

========================

1. Today’s designs only share a few designs among channels. Each RF signal has its dedicated hardware from lower layer PHY (PMD), including baseband, RFA, PA/LNA, filters, switches, and antennas, among others. When the total number of independent channels increases, the DC power consumption efficiency becomes low. Moreover, the complexity of PCB level tuning becomes much more difficult with an increasing number of RF chains.

pic1 Single Channel Tx/Rx example for today’s RF design

2. The Tx Architect of tomorrow aims to save approximately 40% of power consumption compared to today’s designs, resulting in a significant improvement in PCB level complexity and BOM cost. This improvement is mainly due to the removal of the post-PA complex RF switch/filter/n-plexer insertion loss (2.5~3dB).

pic2 Multi Channel Tx tomorrow’s RF design

3. In the next 10 years, the Universal Tx Architect aims to sum the baseband (simulation of which can be done today on Matlab or SystemVue) of all the post-CFR data streams, after which the whole DPD function is applied to the combined baseband signal. This design will require a sample rate of 10-20G/s with 18-19 bits A-to-D conversion. Power consumption of the A-to-D converter at 10G/s needs to be reduced to the equivalent level of today’s 1G/s design.

pic3 Universal Tx Architect for future design

========================

Introduction. Negative delay could remove frequency-dependent wide band load-matching issues, and if achieved, the impact could be huge. However, in reality, L/C/line components all have positive delay. In the past, many of us have tried to use a network’s positive phase vs. frequency feature to achieve negative delay, but all attempts have failed with significant insertion loss.

1. What if we could achieve negative delay from a signal source using a digital approach, such as an FFT-based phase shift algorithm? I have tried a few ideas, but they all failed. The reason for my failure is that traditional FFT approaches can only manipulate I/Q amplitude and phase with voltage. However, the RF matching challenge lies in the fact that there is a phase shift between I and V due to impedance Z = R + jX. The reactance of Z shifts the V/I phase, which makes power delivery from point A to point B less efficient. In the worst case, 100% reflection could occur. So my first attempt at using an FFT approach to solve the matching issue failed.

pic1 Failed idea, digital pre-delay at LO/Mixer stage

2. The next step idea.

pic2 thinking…

========================